Sunday, December 14, 2014

RAM Upgrade

Someone has just pointed out to me that he Nexys4 board that the C65GS project is based on is about to receive a modest upgrade in the form of switching from the 16MB cellular RAM to a 128MB DDR2 RAM module:

http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,1301,1319&Prod=NEXYS4DDR

Reading through the new reference manual for the Nexys4 DDR, I discover the following:

The Nexys4 DDR is an incremental update to the Nexys4 board. The major improvement is the replacement of the 16 MiB CellularRAM with a 128 MiB DDR2 SDRAM memory. Digilent will provide a VHDL reference module that wraps the complexity of a DDR2 controller and is backwards compatible with the asynchronous SRAM interface of the CellularRAM, with certain limitations. See the Nexys4 DDR page at www.digilentinc.com for updates.
Furthermore, to accommodate the new memory, the pin-out of the FPGA banks has changed as well. The constraints file of existing projects will need to be updated. 
The audio output (AUD_PWM) needs to be driven open-drain as opposed to push-pull on the Nexys4.
So overall the changes look relatively small, and it shouldn't be hard to port the design to the new board.

The actual DDR2 memory part is a MT47H64M16HR-25:H, which is capable of 667MB/sec, but according to the reference manual the practical limit will be 650MHz.  Xilinx have a memory interface generator which should make it fairly easy to interface to this RAM, although DDR memory is inherently more complex.

I will likely implement a very small cache, perhaps 8 or 16 bytes, because although the DDR2 RAM has a bandwidth of 650MB/sec, the random-access latency of DDR memory is typically fairly high, and it will be important to avoid incurring this latency on every slowram memory access.

Taking a quick look at the data sheet for the DDR RAM, it looks like the actual speed is 650MT/sec, i.e., 650 mega-transactions per second. I have done some reading on DDR and DDR2 RAM lately, but will need to sit down with the actual memory specifications to work out what this all means in practice.

What is almost certain is that the DDR2 RAM could drive a linear frame buffer if I wanted to, but as I have discussed on the mailing list, a linear frame buffer doesn't fit my definition of an 8-bit style computer.  However, there is already 128MB of address space already reserved for slowram expansion, so it will be quite straight-forward to incorporate it.

Friday, December 12, 2014

LCD Screen Test

I had a little time this evening so I unpacked the LCD panel and driver and hooked it all up to see if it works.  The beginning looked something like:



 The VGA lead is connected to the C65GS FPGA board. And again from above:


So then I tried to turn it on, which, pleasingly resulted in the back-light illuminating, but sadly not in any picture.


So flip the panel over and check that everything is properly connected with the data cable:


The panel end of the cable wasn't quite in properly, but once it was then things were happy:


The next steps for laptopification are now likely to be in the direction of designing a 3D CNC millable case, that can hold the screen, FPGA board, keyboard and other components.  This is where I step outside my current expertise.  If anyone is interested in helping to design the case, I would welcome their assistance.

Thursday, December 11, 2014

Some parts for laptop prototyping have arrived

I have been away on holidays with the family for a couple of weeks, so haven't really touched the C65GS during that time.  

However, just before we flew out I ordered a 15.4" 1920x1200 LCD panel and driver circuit from China to use for laptop prototyping. China air-mail is outrageously cheap to Australia if you don't mind waiting 2 - 6 weeks for delivery.  Since I was going to be away, I figured I could wait.  

So after letting our local post office know that they might need to hold the parcels a bit longer than usual in the unlikely chance that they would turn up early.  

And turn up early they did -- at around 2 weeks including the dispatch time from the suppliers.  Of course, in theory air mail (and sea mail for that matter) from China to Australia should be fast, since we are in the same general part of the world, and their are multiple direct China-Australia flights and sea freight routes.

Here are the two boxes before un-packing:


First, I opened the little one which contains the panel driver:


Then the big one with the 15.4" panel:



The panel is a bit smaller than I expected, being only just larger than the dimensions of my 13" MacBook Pro.  The difference is mostly due to the really fat bezel on the MacBook Pro.


This all makes me happy, because I really want the C65GS laptop to be as compact as possible, especially since I know that it will have to be about 4cm - 5cm thick to fit the full-travel keys, FPGA board and other components in.

I got my genuine C65 keyboard out to see how it compares in width: The screen is only a couple of centimetres wider than the keyboard, so just about perfect.


The next step is to get a 12v UBEC or other power supply so that I can hook the panel and driver up and test that they work.